Xilinx, Inc. — 2 prefixes (MA-L)

Xilinx registers two distinct MA-L OUI blocks under slightly different name spellings — "Xilinx" at 00:0A:35 and "Xilinx, Inc" at 00:5D:03 — both tied to the company's longtime San Jose, CA headquarters at 2100 Logic Drive. Xilinx invented the field-programmable gate array (FPGA) in 1984 and became AMD's largest-ever acquisition when the deal closed in February 2022; the IEEE registry rows for both blocks still carry the pre-acquisition "Xilinx" name rather than AMD, which is expected since IEEE assignee names do not update automatically on corporate acquisition. Unlike a bare single-OUI shell registration, Xilinx has real, checkable device context: AMD's own documentation shows Alveo data-center FPGA accelerator cards shipping with 00:0A:35-prefixed default MACs, the AXI Ethernet Lite MAC IP core (embedded in Zynq and Zynq UltraScale+ SoC designs) is configured with vendor MAC addresses drawn from these blocks per AMD's support guidance, and Xilinx's own xbtest board-diagnostic tooling allocates test MAC addresses from the 00:0A:35 pool. A LAN sighting of either prefix most plausibly indicates FPGA development hardware, a data-center accelerator card, or an embedded system built around a Xilinx/AMD FPGA SoC rather than a consumer device.

IEEE assignments

two MA-L blocks — 00:0A:35 ("Xilinx", 2100 Logic Drive, San Jose, CA 94110, US) and 00:5D:03 ("Xilinx, Inc", 2100 Logic drive, San Jose, CA 95124, US) [Confirmed] — the IEEE MA-L registry, the IEEE MA-L registry, the Wireshark manufacturer database, the Wireshark manufacturer database

Registry / block size

both MA-L (24-bit OUI, ~16.7M addresses each); no MA-M (the IEEE MA-M registry) or MA-S (the IEEE MA-S registry) blocks found under any Xilinx-named organization [Confirmed] — the IEEE MA-M registry, the IEEE MA-S registry (absence checked)

HQ / address

2100 Logic Drive, San Jose, CA, US — registry rows show two slightly different ZIPs (94110 vs 95124) for the same street address, an IEEE registry data inconsistency rather than two locations [Confirmed] — IEEE MA-L (rows above)

Company status

Xilinx became a wholly-owned subsidiary of AMD in Feb 2022 (largest AMD acquisition to date); IEEE registry rows are unchanged and still read "Xilinx" / "Xilinx, Inc" — this is normal for acquired companies since IEEE does not retroactively rename OUI assignees

[Confirmed] — https://docs.amd.com/r/en-US/pg135-axi-ethernetlite/Ethernet-MAC-Address

Device / usage context

FPGA and adaptive-SoC hardware, not typical consumer devices — Alveo data-center accelerator cards default to a 00:0A:35-prefixed MAC; the AXI Ethernet Lite MAC IP core (used in Zynq/Zynq UltraScale+ embedded-Ethernet FPGA designs) is provisioned with per-board MACs per AMD's own guidance; xbtest board-test tooling draws test MACs from the 00:0A:35 pool [Likely] — https://docs.amd.com/r/en-US/pg135-axi-ethernetlite/Ethernet-MAC-Address, https://www.xilinx.com/support/answers/53476.html, https://xilinx.github.io/xbtest/doc/main/user-guide/build/html/docs/test-cases/gt-mac-test-case-description.html, https://github.com/Xilinx/xup_vitis_network_example/issues/10

Security context

no MAC/OUI-specific vulnerabilities found. Unrelated silicon-level findings exist on Xilinx FPGA bitstream security — "Starbleed" (7-Series bitstream-decryption oracle) and "JustSTART" (RSA-authentication bypass on UltraScale/UltraScale+) — relevant as general FPGA config-security context, not to the OUI itself

[Confirmed] — https://www.usenix.org/conference/usenixsecurity20/presentation/ender, https://arxiv.org/pdf/2402.09845

Date provenance

IEEE publishes no assignment/registration date for either block (the IEEE MA-L registry / the Wireshark manufacturer database carry no date column); no date is recorded here, and any "date registered" shown on third-party lookup sites is a database-scrape artifact, not an IEEE fact

[Confirmed] — the IEEE MA-L registry, the Wireshark manufacturer database

Related vendors

AMD (parent company since Feb 2022 acquisition) [Confirmed] — https://docs.amd.com/r/en-US/pg135-axi-ethernetlite/Ethernet-MAC-Address